index - Equipe Secure and Safe Hardware

 

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Mots clés

Countermeasures Convolution Routing Neural networks Authentication Protocols Receivers Robustness Switches Process variation Fault injection attack Dynamic range Field programmable gate arrays Writing Information leakage Intrusion detection Differential Power Analysis DPA FPGA Hardware security Reverse-engineering Temperature sensors EMFI Coq Voltage Circuit faults Magnetic tunneling Gem5 Machine learning Side-Channel Analysis Simulation Energy consumption Confusion coefficient OCaml Random access memory Training SoC Field Programmable Gates Array FPGA Elliptic curve cryptography Security TRNG PUF Costs Spin transfer torque Countermeasure Image processing Power-constant logic Side-Channel Analysis SCA Fault attacks 3G mobile communication Internet of Things AES Side-channel analysis Randomness Power demand Defect modeling Reliability MRAM RSA Fault injection Side-channel attacks Formal methods Reverse engineering CRT Asynchronous Security services STT-MRAM FDSOI Loop PUF Magnetic tunnel junction Aging GSM Application-specific VLSI designs Linearity Side-Channel Attacks Logic gates Formal proof Dual-rail with Precharge Logic DPL Resistance Signal processing algorithms Filtering Electromagnetic Security and privacy Masking countermeasure Differential power analysis DPA Computational modeling SCA Cryptography Masking Sensors ASIC Transistors Estimation Side-channel attacks SCA Hardware Lightweight cryptography Memory Controller DRAM Side-channel attack Mutual Information Analysis MIA CPA

 

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216

Références bibliographiques

431

Open access

42 %

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